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74AUP1G96FHX
- Manufacturer’s Part#:74AUP1G96FHX
- Manufacturer:
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- Series:74AUP
- ECAD Model:
- Description:IC UNIV O/D GATE 6-MICROPAK2
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- Quantity:RFQAdd to RFQ List
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- In Stock: 804485
- Available: 14
Reference Price(In US Dollars)
| Qty | Unit Price | Ext.Price |
|---|---|---|
| 1+ | US $0.34875 | US $0.35 |
| 10+ | US $0.23250 | US $2.33 |
| 30+ | US $0.17438 | US $5.23 |
| 100+ | US $0.13950 | US $13.95 |
| 500+ | US $0.12788 | US $63.94 |
| 1000+ | US $0.11625 | US $116.25 |
Do you want a lower wholesale price? Please send us an inquiry, and we will respond immediately.
- Description
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- Shopping Guide
The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
Features
• Wide supply voltage range from 0.8 V to 3.6 V
• High noise immunity
• Complies with JEDEC standards: ◆ JESD8-12 (0.8 V to 1.3 V) ◆ JESD8-11 (0.9 V to 1.65 V) ◆ JESD8-7 (1.2 V to 1.95 V) ◆ JESD8-5 (1.8 V to 2.7 V) ◆ JESD8-B (2.7 V to 3.6 V)
• ESD protection: ◆ HBM JESD22-A114-D exceeds 5000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V
• Low static power consumption; ICC = 0.9 µA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• Input-disable feature allows floating input conditions
• IOFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from −40 °C to +85 °C and −40 °C to +125 °C
Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.
SHIPPING GUIDE
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