EP2S60F672I4
- Manufacturer’s Part#:EP2S60F672I4
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- Series:Stratix® II
- ECAD Model:
- Description:IC FPGA 492 I/O 672FBGA
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- Quantity:RFQAdd to RFQ List
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- In Stock: 7400
- Available: 55
Reference Price(In US Dollars)
Qty | Unit Price | Ext.Price |
---|---|---|
1+ | US $117.00000 | US $117.00 |
10+ | US $91.00000 | US $910.00 |
30+ | US $78.00000 | US $2340.00 |
100+ | US $71.50000 | US $7150.00 |
500+ | US $68.90000 | US $34450.00 |
1000+ | US $65.00000 | US $65000.00 |
Do you want a lower wholesale price? Please send us an inquiry, and we will respond immediately.
- Description
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- Shopping Guide
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions.
Features
The Stratix II family offers the following features:
• 15,600 to 179,400 equivalent LEs; see Table 1–1
• New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
• Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
• TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
• High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
• Up to 16 global clocks with 24 clocking resources per device region
• Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
• Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
• Support for numerous single-ended and differential I/O standards
• High-speed differential I/O support with DPA circuitry for 1-Gbps performance
• Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
• Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
• Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
• Support for design security using configuration bitstream encryption
• Support for remote configuration updates
Functional Equivalent (FE) materials, including Fused Filament Fabrication (FFF) form, assembly, and functionally compatible substitute materials.
SHIPPING GUIDE
Shipping Methods
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Shipping Cost
Shipping starts at $40 but varies for destinations like South Africa, Brazil, India, and more. The actual shipping charges depend on time zone, country, and package weight/volume.
Delivery Time
We ship orders once daily, around 5 p.m., except on Sundays. The estimated delivery time may vary depending on the courier service you choose, but typically ranges from 5 to 7 business days.
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