LC87F7NP6AVUEJ-2H

Features Flexible Logic Architecture
• Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os Ultra Low Power Devices
• Advanced 65 nm low power process
• As low as 19 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options Embedded and Distributed Memory
• Up to 240 Kbits sysMEM™ Embedded Block RAM
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic On-Chip User Flash Memory
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2C and JTAG interfaces
• Can be used as soft processor PROM or as Flash memory Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with DQS support High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL –PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode