LFEC6E-3QN208I

Introduction
The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECPDSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip.
The LatticeEC™ (EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to achieve lower cost solutions.
Features
• Extensive Density and Package Options
• 1.5K to 32.8K LUT4s
• 65 to 496 I/Os
• Density migration supported
• sysDSP™ Block (LatticeECP™ Versions)
• High performance multiply and accumulate
• 4 to 8 blocks − 4 to 8 36x36 multipliers or
– 16 to 32 18x18 multipliers or − 32 to 64 9x9 multipliers
• Embedded and Distributed Memory
• 18 Kbits to 498 Kbits sysMEM™ Embedded Block RAM (EBR)
• Up to 131 Kbits distributed RAM
• Flexible memory resources: − Distributed and block memory
• Flexible I/O Buffer
• Programmable sysI/O™ buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL − SSTL 3/2 Class I, II, SSTL18 Class I − HSTL 18 Class I, II, III, HSTL15 Class I, III − PCI − LVDS, Bus-LVDS, LVPECL, RSDS
• Dedicated DDR Memory Support
• Implements interface up to DDR400 (200MHz)
• sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting
• System Level Support
• IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability
• SPI boot flash interface
• 1.2V power supply
• Low Cost FPGA
•
Features optimized for mainstream applications
• Low cost TQFP and PQFP packaging