MC100E143FNR2

The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind.
The E143 holds current data or loads new data, with the nine inputs D0 − D8 accepting parallel input data.
The SEL (Select) input pin is used to switch between the two modes of operation − HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
The 100 Series contains temperature compensation
Features
• 700 MHz Min. Operating Frequency
• 9-Bit for Byte-Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V
• NECL Mode Operating Range: VCC= 0 V with VEE = −4.2 V to −5.7 V
• Internal Input 50 k Pulldown Resistors
• ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V
• Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
• Transistor Count = 484 devices
• Pb−Free Packages are Available
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