MC100LVEL34DG

The MC100LVEL34 is a low skew ÷ 2, ÷ 4, ÷ 8 clock generation chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.
The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open
Features
• 50 ps Typical Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 1.5 GHz Toggle Frequency
•
The 100 Series Contains Temperature Compensation.
• PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V
• Open Input Default State
• LVDS Input Compatible
•
These are Pb−Free Devices