PEB2255H-V13

The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a monolithic CMOS device which implements the analog receive and transmit line interface functions to primary rate PCM carriers. It may be programmed or hard wired to operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems.
Features
• ISDN line interface for 1544 and 2048 kbit/s (T1 and CEPT)
• Data and clock recovery
• Transparent to ternary codes
• Low transmitter output impedance for a high return loss with reasonable protection resistors (CCITT G.703 requirements for the line input return loss fulfilled)
• Adaptively controlled receiver threshold
• Programmable pulse shape for T1 applications
• Jitter specifications of CCITT I.431 and BELLCORE TR-NWT-000499 publications met
• Wander and jitter attenuation
• Jitter tolerance of receiver: 0.5 UI s
• Implements local and remote loops for diagnostic purposes
• Monolithic line driver for a minimum of external components
• Low power, reliable CMOS technology
• Loss of signal indication for receiver
• Clock generator for system clocks