TLC252CDR

The STLC2500 is a single chip ROM-based Bluetooth solution implemented in 0.13 m ultra low power, low leakage CMOS technology for applications requiring integration up to HCI level. Patch RAM is available enabling multiple patches/upgrades.
The STLC2500s main interfaces are UART for HCI transport, PCM for voice and GPIOs for control purposes.
The Radio is designed for the single chip requirement and for drastic power consumption reduction.
FEATURES
• Bluetooth™ specification compliance: V1.1 and V1.2
• Ericsson Licensing Technology Baseband Core (EBC)
• Point-to-point, point-to-multi-point (up to 7 slaves) and scatternet capability
• Asynchronous Connection Oriented (ACL) logical transport link
• Synchronous Connection Oriented (SCO) link: 2 simultaneous SCO channels
• Support Pitch-Period Error Concealment (PPEC)
– Improves speech quality in the vicinity of interference
– Improves coexistence with WLAN
– Works at receiver, no Bluetooth implication
• Adaptive Frequency Hopping (AFH): hopping kernel, channel assessment as Master and as Slave
• Faster Connection: Interlaced scan for Page and Inquiry scan, first FHS without random back off, RSSI used to limit range
• Extended SCO (eSCO) links
• HW support for packet types
– ACL: DM1, 3, 5 and DH1, 3, 5
– SCO: HV1, 3 and DV
– eSCO: EV3, 5
• Clock support
– System clock input (digital or sine wave) at 13, 26, 19.2 or 38.4 MHz
– LPO clock input at 3.2, 16.384, 32 or 32.768 kHz
• ARM7TDMI CPU
– 32-bit Core
– AMBA (AHB-APB) bus configuration
• Patch RAM capability
• Memory organization
– On chip RAM, including provision for patches
– On chip ROM, preloaded with SW up to HCI
• Communication interfaces
– Fast UART
– PCM interface
– 4 programmable GPIOs
– External interrupts possible through the GPIOs
– Fast master I2C interface
• Efficient support for WLAN coexistence in collocated scenario
• Ciphering support up to 128 bits key
• Software support
– Lower level stack (up to HCI)
– HCI Transport Layer: H4 (including proprietary extensions)
– HCI proprietary commands (e.g. peripherals control)
– Single HCI command for patch/upgrade download
• Single power supply with internal regulators for core voltage generation
• Supports 1.65 to 2.85 Volts IO systems
• Total number of external components limited to 7 (6 decoupling capacitors and 1 filter) thanks to:
– Fully integrated synthesizer (VCO and loop filter)
– Integrated antenna switch
– Low IF receiver
• Auto calibration (VCO, Filters)
• No need for calibration of the RF part
• Timer and watchdog
• Power class 2 compatible
• Ultra low power architecture with 3 different low power levels:
– Sleep Mode
– Deep Sleep Mode
– Complete Power Down Mode
• Software Initiated Low Power Mode
• Dual Wake-up mechanism: initiated either by the Host or by the Bluetooth device
• Standard TFBGA-84 pins package