XC3S50A-4TQG144I

XC3S50A-4TQG144I Description  
The Xilinx XC3S50A-4TQG144I family of FPGAs uses advanced 90nm process technology to achieve high system performance while reducing configuration costs. XC3S50A-4TQG144I is one of the devices in this family, featuring 108 inputs/outputs in a compactly sized TAFP-144 enclosure. This FPGA is specified for operation from -40°C to 100°C.   XC3S50A-4TQG144I
Features  
• Very low cost, high-performance logic solution for high-volume, cost-conscious applications
• Dual-range VCCAUX supply simplifies 3.3V-only design
• Suspend, Hibernate modes reduce system power
• Multi-voltage, multi-standard SelectIO™ interface pins- Up to 502 I/O pins or 227 differential signal pairs- LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling- Selectable output drive, up to 24 mA per pin- QUIETIO standard reduces I/O switching noise- Full 3.3V ± 10% compatibility and hot swap compliance- 640+ Mb/s data transfer rate per differential I/O- LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors- Enhanced Double Data Rate (DDR) support- DDR/DDR2 SDRAM support up to 400 Mb/s- Fully compliant 32-/64-bit, 33/66 MHz PCI® technology support
• Abundant, flexible logic resources- Densities up to 25,344 logic cells, including optional shift register or distributed RAM support- Efficient wide multiplexers, wide logic- Fast look-ahead carry logic- Enhanced 18 x 18 multipliers with optional pipeline- IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture- Up to 576 Kbits of fast block RAM with byte write enables for processor applications- Up to 176 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)- Clock skew elimination (delay locked loop)- Frequency synthesis, multiplication, division- High-resolution phase shifting- Wide frequency range (5 MHz to over 320 MHz)
• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs- Low-cost, space-saving SPI serial Flash PROM- x8 or x8/x16 BPI parallel NOR Flash PROM- Low-cost Xilinx® Platform Flash with JTAG- Unique Device DNA identifier for design authentication- Load multiple bitstreams under FPGA control- Post-configuration CRC checking
• Complete Xilinx ISE® and WebPACK™ development system software support plus Spartan-3A Starter Kit
• MicroBlaze™ and PicoBlaze embedded processors
• Low-cost QFP and BGA packaging, Pb-free options- Common footprints support easy density migration- Compatible with select Spartan-3AN nonvolatile FPGAs- Compatible with higher density Spartan-3A DSP FPGAs
• XA Automotive version available   XC3S50A-4TQG144I Applications  
• Wireless Communication
• ASIC Prototyping
• Security Systems
• High-end consumer products