XC6SLX4-2TQG144I

XC6SLX4-2TQG144I Description
The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications.
The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks.
These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power optimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection.
These features provide a low cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. XC6SLX4-2TQG144I
Features -3, -3N, -2, -1L (LX)/-3, -3N, -2 (LXT) speed grades with 0 to 85°C and -40 to 100°C temperatureSmall form factor packaging, MicroBlaze™ soft processor, diverse number of supported I/O protocolsAdvanced power management, SelectIO™ interface technology, 18Kb (2 x 9Kb) block RAMsSpartan®-6 provides increased system performance with up to 8 low power 3.2Gb/s serial transceivers800Mb/s DDR3 with integrated memory controller, zero power with hibernate power-down modeBOM cost reduction, clock management tile (CMT) for enhanced performanceAuto detect configuration options and enhanced IP security with AES and device DNA protectionEnabled by ISE® design suite (no cost, front to back FPGA design solution for Linux and Windows)1.14 to 1.26V (-3, -3N, -2), 0.95 to 1.05V (-1L) internal supply voltage (standard performance)Lower power 1V core voltage (LX/-1L), high performance 1.2V core voltage (LX, LXT/-2, -3, -3N)